
1. Technology overview
Quadric, Inc. is a semiconductor IP licensing company headquartered in Burlingame, California. It licenses AI processor designs that let chip makers and system companies run inference on devices and at the edge, and its first proof-of-concept test chip dates from 2021.
The Chimera GPNPU is a fully programmable, synthesizable NPU core that combines a Von Neumann design with a 2D SIMD matrix array and has no fixed-function blocks. ONNX graphs and C++ code compile into one binary through the Chimera SDK. Configurations scale from 1 to 6,912 INT8 TOPS, and DENSO and TIER IV are named as customers.
2. Highlighted features & specifications
- Programmable GPNPU: hybrid Von Neumann plus 2D SIMD core with a 7-stage in-order pipeline and no fixed-function blocks.
- Product family: QC-Nano, QC-Perform, QC-Ultra, QC-Multi and Multi-Cluster, from 1 to 6,912 INT8 TOPS.
- Chimera SDK: Graph Compiler, ChiPy Python interface, C++ library, LLVM compiler and instruction set simulator.
- Model coverage: ONNX graphs including YOLO, BERT, ViT, Whisper and LLaMA, plus custom C++ operators.
- Memory options: L2 data memory from 1 MB to 16 MB and configurable AXI interfaces.
- DevStudio: cloud access to the SDK, datasheets, benchmarks and 350+ curated models.
3. Potential application
A Vietnamese fabless start-up designing a camera or smart-home SoC can license a QC-Nano or QC-Perform core to run vision models. An automotive electronics supplier can use multi-core configurations for ADAS perception. A robotics or industrial-sensor maker can port custom C++ operators without redesigning hardware.
4. Benefits
A single programmable core and toolchain covers vision models and LLMs, so chip designers are less exposed to model changes after tape-out. New operators can be added as C++ kernels instead of new hardware. The same architecture scales from sub-1W cores to multi-cluster designs, and a cycle-accurate simulator supports early performance planning.
5. Market trends & opportunities
Edge devices, AI PCs, cars and industrial sensors increasingly need to run transformers and on-device LLMs on silicon designed years earlier. Licensable, fully programmable NPU IP addresses that model-roadmap risk. Vietnamese and Southeast Asian fabless and electronics firms that design their own SoCs can license such IP rather than build an NPU in-house.
6. Other information
Headquartered at 270 East Ln, Burlingame, California. Raised a USD 30 million Series C in January 2026 and extended it to USD 46 million in July 2026, led by IFC, for USD 90 million total capital. Chimera GPNPU was named 2025 Edge AI & Vision Product of the Year. The old domain quadric.io now redirects to quadric.ai, the company's own site.
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