Bronco Core AI Agents for Chip Verification

Bronco AI is a San Francisco applied AI lab founded in 2023 and part of Y Combinator's Summer 2023 batch. It builds AI verification engineers for chip design, targeting the debug, testbench and coverage work that delays tape-out.

The Bronco Core platform combines frontier and custom-trained models, a self-improving reasoning system, a knowledge base and AI-native EDA tooling for waveforms, RTL and simulation. Agents on top review large specifications and pressure-test verification plans, generate UVM collateral, RTL and SVA assertions, investigate failures across waves, logs, RTL and specs from block level to SoC, bucket nightly regression failures and close remaining coverage with targeted stimulus. Customers can also build their own agents on the same core. The company states it is deployed with publicly traded chip companies and startups, including teams working on 4 nm designs.

• Simulation debug: automatic failure-to-fix on waveforms over 100 GB, from block level to SoC.
• Regression triage: nightly failures bucketed into unique signatures and auto-assigned.
• RTL and assertion generation: new blocks, fixes and SVA derived from spec and waves, checked against simulation.
• Spec review: reads large specifications, flags ambiguities and pressure-tests verification plans.
• Coverage closure: targeted stimulus for unhit coverage bins, traced back to the spec.
• Flexible deployment: on-premise or bring-your-own-AI, native to standard EDA flows.

A Vietnamese verification services team can use regression triage and debug agents to handle nightly failures for overseas customers. A design centre working on SoC projects can use spec review to catch ambiguities before testbench bring-up. A fabless startup can close coverage gaps faster before tape-out.

Multi-day simulation debugs can be reduced to about 15 minutes, according to the company. Nightly failures are grouped into unique signatures and auto-assigned before verification engineers start work. Coverage closure continues past the roughly 80% level where regressions usually plateau. On-premise deployment keeps design IP inside the customer environment.

Verification takes the largest share of chip project effort, and experienced verification engineers are scarce. AI agents that run inside existing EDA flows are becoming a practical way to raise productivity without exposing design IP. Vietnam's growing pool of junior chip engineers creates demand for tools that speed up debug and coverage work.

Founded in 2023 in San Francisco by David Zhi LuoZhang and Jeffrey Pan; Y Combinator Summer 2023 batch. Backed by 8VC, Elad Gil, SV Angel and YC. Exhibited at DAC 2026 in Long Beach (booth 935).