Normal EDA AI-Native Chip Verification

Normal Computing Corporation is a New York-based applied AI company founded in 2022 that builds AI-native EDA software and AI-co-designed silicon. It addresses the cost and time of verifying complex IP and SoCs, where turning specifications into complete test plans and testbenches is still largely manual.

Normal EDA uses auto-formalizing AI that combines language models with formal logic to build a mathematical model of a design specification. From text, truth tables, timing diagrams and command sequences, it generates structured test plans linked to the exact spec passages, then produces SystemVerilog/UVM testbench code that runs on VCS and Xcelium. Engineers review and refine results in a human-in-the-loop workflow, and collateral is updated automatically when the spec changes. The company states its products are in production with large semiconductor companies.

• Test plan generation: builds structured, spec-linked test plans targeting full functional coverage, exportable as CSV.
• Testbench code generation: produces SystemVerilog/UVM code for integration into existing testbenches.
• Auto-formalization: converts specifications into a logically consistent formal model.
• Multimodal input: interprets timing diagrams and waveform images to derive stimulus and checks.
• Traceability and revision handling: links tests to the spec and updates collateral on design changes.
• Human-in-the-loop review: engineers approve, flag edge cases and give real-time feedback.

A Vietnamese design verification service provider can generate spec-traced test plans and UVM code for memory or interface IP. An automotive electronics team in Vietnam can use traceability to support safety audits of controller chips. Training centres can use the platform to teach specification-driven verification.

Test plans are traced to the exact quotes, tables and diagrams in the specification, which simplifies reviews and audits. Verification collateral updates automatically when the design is revised, reducing rework. Generated SystemVerilog/UVM code fits into existing testbenches and simulators. The company says its approach can bring custom silicon to market about twice as fast.

Specification-driven verification and formal methods combined with large language models are gaining traction as SoCs grow more complex and verification teams struggle to keep up. Major chipmakers are investing in AI-native EDA, as shown by Samsung Catalyst's backing. Vietnam's chip design ecosystem can use such tools to raise verification quality for export-oriented projects.

Founded in 2022; headquartered at 27 W 20th Street, New York. Raised USD 50 million in March 2026 in a strategic round led by Samsung Catalyst Fund, with total funding above USD 85 million. Taped out CN101, described as a thermodynamic computing chip, in 2025. Founding member of the Si2 LLM Benchmarking Coalition. SOC 2 compliance is a stated priority.