Semidynamics Cervell RISC-V NPU IP & AI Inference Stack

Semidynamics is a RISC-V processor IP company founded in 2016 in Barcelona, Spain, led by founder and CEO Roger Espasa, with more than 150 employees. It addresses the memory and data-movement bottlenecks that limit AI inference performance and the lock-in of proprietary processor architectures.

Its Cervell NPU IP uses an All-In-One RISC-V design that combines CPU, vector and tensor units under a single instruction set, configurable from 8 to 64 TOPS in C1, C8 and C32 variants and supporting INT4 to FP64 data types. The IP portfolio also includes the Atrevido A426 CPU core and Gazzillion Misses memory technology, which tracks many outstanding cache misses so compute does not stall. The Aliado software suite provides an IDE, toolchain, kernel library, emulator and model zoo. In 2026 the company extended into 3 nm inference silicon, boards and rack-scale systems.

• Cervell NPU: All-In-One RISC-V core combining CPU, vector and tensor units, configurable from 8 to 64 TOPS.
• Variants: C1 for real-time edge inference, C8 for high throughput and C32 for clustered scaling.
• Data types: INT4 to INT64 and FP16, BF16, FP32 and FP64 options.
• Atrevido A426 CPU: scalable RISC-V core for mixed compute and parallel math.
• Gazzillion Misses: memory technology that keeps many cache misses in flight to avoid stalls.
• Aliado software: IDE, toolchain, kernel library, emulator and model zoo.

A Vietnamese fabless company can license Cervell C1 to add on-device AI to a camera or IoT SoC. A local chip design centre can build an AI accelerator around clustered Cervell cores for telecom or data centre use. A university lab can use the Aliado emulator and toolchain for RISC-V AI research and training.

A single RISC-V instruction set covers control, vector and tensor work, so one software stack serves the whole NPU. Throughput scales from compact edge configurations to clustered data centre deployments. Configurable data types from INT4 to FP64 let designers balance accuracy and efficiency. An open ISA avoids lock-in to proprietary processor architectures.

RISC-V is gaining ground as an open alternative for AI processors, and inference workloads are increasingly limited by memory bandwidth rather than raw compute. Countries building domestic chip capability favour licensable, open-ISA IP. Vietnam's chip design programmes and Southeast Asian edge AI device makers are natural users of configurable RISC-V NPU IP.

Founded in 2016 in Barcelona, Spain, by CEO Roger Espasa; more than 150 employees. SK hynix made a strategic investment in 2026. Taped out a 3 nm chip with TSMC in December 2025 and announced a cooperation with SiPearl on a European rack-scale AI platform in May 2026. Holds the Spanish PYME Innovadora seal valid to 2029.