Agnisys IDesignSpec Specification Automation Suite

Agnisys is an EDA company with its corporate office in Garland, Texas, and about two decades of experience in specification automation. It addresses the error-prone manual work of keeping register maps, RTL, verification models, software headers and documentation consistent across a chip project.

The IDesignSpec suite takes one executable specification, imported from IP-XACT, SystemRDL, Excel, Word, CSV, JSON, YAML or XML, and generates register and memory RTL, CDC and DFT logic, IP connectivity, UVM register models and testbenches, C/C++ headers, bare-metal software environments and HTML, PDF or Word documents. Newer modules include IDS-AI, an agentic framework from specification to verification; IDS-NoC, which generates deadlock-free network-on-chip RTL; and design-aware test points for DFT. The suite is described as ISO 26262 certified.

• Executable specification: import from IP-XACT, SystemRDL, spreadsheets and documents into one source.
• RTL generation: registers, memories, CDC logic, DFT and IP connectivity.
• Verification collateral: UVM register models, testbenches and AI-assisted tests.
• Software and documents: C/C++ headers, memory maps, bare-metal environments and HTML/PDF/Word output.
• IDS-NoC: generation of scalable, deadlock-free network-on-chip fabrics in SystemVerilog.
• IDS-AI: agentic framework covering specification, RTL generation and verification.

A Vietnamese SoC team can generate register RTL, UVM models and firmware headers from one spreadsheet-based specification. A design services company can deliver consistent documentation to customers alongside RTL. An automotive chip project can use the ISO 26262 certified flow for safety-related register blocks.

A single specification keeps hardware, verification, software and documentation teams in sync and reduces mismatch bugs. Generated UVM models and tests cut manual verification effort for registers and memories. Early adopters of design-aware test points report up to 4x better test coverage per flip-flop and 50% fewer top-level ATPG patterns. ISO 26262 certification supports automotive projects.

SoCs now contain thousands of registers and complex on-chip networks, and specification changes ripple across hardware, firmware and documentation. Specification-driven automation and AI agents are being adopted to keep these artefacts consistent. Growing chip design teams in Vietnam and Southeast Asia benefit from tools that standardise these flows from the start.

EDA company with its corporate office in Garland, Texas, and about two decades of experience. Product suite described as ISO 26262 certified with a TUV mark. Testimonials from iCatch Technology, Etched and Wacom. Exhibited at DAC 2026 with a DFT talk co-presented with Google.