Axiomise Formal Verification Apps & Services

Axiomise is a formal verification company founded in 2017 in the UK by Dr. Ashish Darbari and Dr. Vidya Chandran Darbari. It aims to make formal verification mainstream, so chip teams can prove designs correct exhaustively instead of relying only on simulation, which can miss corner-case bugs.

Its axiomiser platform hosts configurable apps: formalISA for automated formal verification of RISC-V processors, nocProve for custom network-on-chip implementations, footprint for silicon area analysis and floatrix. Apps check Verilog or VHDL designs against SystemVerilog Assertions, and the CoreProve abstraction engine helps bounded proofs converge. The company also provides formal verification services for SoC sign-off and RISC-V cores, consulting and training, and has worked with more than 20 customers and Bluespec.

• formalISA: automated formal verification app for RISC-V processor cores.
• nocProve: formal sign-off of custom network-on-chip designs, configurable for protocols and routing rules.
• footprint: silicon area analyser launched in 2025.
• CoreProve engine: abstraction-based proof engine that helps bounded proofs converge.
• Verification services: SoC end-to-end sign-off and RISC-V formal verification.
• Training: on-demand and instructor-led formal verification courses.

A Vietnamese team building a RISC-V microcontroller can use formalISA to check ISA compliance before tape-out. An AI chip startup can sign off its custom NoC with nocProve. A university or design centre can run formal verification training to upskill new verification engineers.

Exhaustive formal proofs find corner-case bugs that simulation can miss in processors and on-chip networks. Ready-made apps reduce the expertise needed to start formal verification on RISC-V cores or NoCs. nocProve is reported to deliver results within hours. Training has reached over 1,600 engineers, helping teams build in-house formal skills.

RISC-V adoption lets many companies design their own processors, which raises the need to verify custom cores thoroughly. AI accelerators rely on complex network-on-chip fabrics where deadlocks and protocol errors are costly. Vietnam and Southeast Asia are investing in RISC-V and chip design training, and formal verification skills remain scarce in the region.

Founded in 2017 and based in London, United Kingdom, by Dr. Ashish Darbari (CEO) and Dr. Vidya Chandran Darbari. Partner of Bluespec for RISC-V core verification. Sponsor of DVCon US, Europe, India and Japan events in 2025 and 2026.