Baum Power Analysis EDA Suite

Baum Design Systems is a South Korean electronic design automation (EDA) company focused on chip power analysis and modeling. It helps SoC teams estimate and reduce power consumption early at the RTL stage, before costly gate-level sign-off, under the theme of shift-left low-power design.

The suite includes PowerSpion, which computes power efficiency metrics from RTL and lints redundant clock-gating cells and is light enough for CI/CD pipelines; PowerBaum, which builds power models from realistic software workloads for use in simulation or emulation; PowerWurzel, a fast gate-level simulation engine; and PowerMesser, an AI-based IP launched in 2025 that measures workload-driven power in real time on chip. Named users include ASICLAND, SiliconArts, FuriosaAI, FADU and Telechips.

• PowerSpion: RTL power efficiency metrics and clock-gating lint without full power analysis.
• PowerBaum: power models built from realistic software workloads for simulation or emulation.
• PowerWurzel: fast gate-level simulation engine supporting RTL and gate-level vectors.
• PowerMesser: AI-based on-chip IP that measures workload-driven power in real time.
• CI/CD integration: lightweight checks designed to run in RTL regression pipelines.
• Emulation support: power models integrate with hardware emulation flows.

A Vietnamese IoT chip team can screen RTL commits for power regressions in its CI pipeline. A design services company can offer customers workload-based power estimates before tape-out. An AI accelerator startup can model power under real neural network workloads to size packaging and cooling.

Power problems are found at RTL, when fixes are cheaper than after synthesis or layout. Workload-based power models reflect real software behaviour rather than synthetic vectors. Lightweight checks fit into continuous integration, so every RTL change can be screened. Customers such as SiliconArts and FuriosaAI have used the suite to reduce GPU and AI chip power.

Power and thermal limits now constrain AI accelerators, mobile SoCs and edge devices as much as performance does. Design teams are shifting power analysis left to RTL to avoid late surprises. Emerging chip design centres in Vietnam and Southeast Asia, which focus on low-power IoT and AI chips, need affordable specialised power tools alongside mainstream EDA.

South Korean EDA company; CEO Seungwhun Paik, a former Synopsys low-power expert. Series A funding led by K Cube Ventures (2017) and a 5 billion won Series A led by LB Investment (2022). Regular sponsor of DVCon Taiwan and exhibitor at DAC.