Baya WeaveIP Fabric & WeaverPro Chiplet Platform

Baya Systems is a Series B semiconductor IP company headquartered in Santa Clara, California, with teams in Austin, Cambridge and Bengaluru. It develops software-driven, chiplet-ready fabric technology that moves data between processors, memory, accelerators and I/O in AI, HPC, automotive and edge chips.

The offering has two parts. WeaverPro is a software platform for system-level modelling, simulation, early validation and data-driven optimisation of fabric and cache architectures, with CacheStudio and FabricStudio tools. WeaveIP is a protocol-agnostic fabric IP portfolio covering coherent, non-coherent, custom and switch fabrics, including NeuraScale for AI scale-up and scale-out, that scales from a single SoC to multi-chiplet systems. Tenstorrent has licensed the technology for its AI and RISC-V chiplet solutions, and Openchip and Kandou AI have announced partnerships.

• WeaverPro platform: system-level modelling, simulation and early validation of fabric and memory architectures.
• CacheStudio and FabricStudio: tools for data-driven optimisation of cache hierarchies and on-chip networks.
• Coherent Fabric: cache-coherent interconnect IP for multi-core and multi-chiplet compute.
• Non-Coherent and Custom Fabric: configurable interconnect for accelerators, memory and I/O subsystems.
• NeuraScale: switching fabric for AI scale-up and scale-out systems.
• Chiplet readiness: one transport layer that scales from a single SoC to multi-die systems.

A Vietnamese ASIC design services company can license WeaveIP to build the on-chip network for customer AI or automotive SoCs. A local chip startup can use WeaverPro to explore cache and fabric trade-offs before RTL. A research team developing RISC-V chiplets can integrate coherent fabric IP for multi-core prototypes.

Architects can model and validate fabric and cache choices in software before committing to RTL, reducing late redesigns. One protocol-agnostic fabric family covers coherent and non-coherent traffic from single SoCs to multi-chiplet systems. Fabric IP is offered with optimised power, area and cost. ISO 9001:2015 certification and a distribution partner in Asia-Pacific support adoption by regional design teams.

AI accelerators and data centre chips are moving to chiplet architectures, where data movement between dies and memory is a key bottleneck. Licensable fabric IP lets smaller design teams build complex SoCs without developing interconnect from scratch. Asia-Pacific design activity is growing, and Vietnam's emerging chip design sector can access such IP through regional ASIC service partners.

Headquartered in Santa Clara, California, with offices in Austin, Cambridge (U.K. office opened November 2025) and Bengaluru, and a Japan expansion in August 2026. Raised a USD 36 million plus Series B in January 2025 led by Maverick Silicon with strategic investment from Synopsys; Matrix Partners and Intel Capital also invested. ISO 9001:2015 certified; EE Times Silicon 100 (2025) and Frost & Sullivan recognition. AdoreSys (Singapore) distributes its IP in China and Asia-Pacific.