Eliyan NuLink Chiplet Interconnect PHY & UMI

Eliyan is a chiplet interconnect company based in Santa Clara, California, founded by Ramin Farjadrad, Patrick Soheili and Syrus Ziai. It builds on a die-to-die interconnect architecture that Farjadrad developed in 2016 and targets the bandwidth, power and packaging-cost limits of multi-die AI and data centre chips.

Its NuLink die-to-die PHY supports BoW, UCIe and proprietary simultaneous bidirectional signalling at bump pitches from 40 to 130 microns, on both silicon interposers (NuLink-AP) and standard organic substrates (NuLink-SP). NuLink-X extends the approach to chip-to-chip links: NuLink-XS for short parallel links on the same board and NuLink-XD based on 224G PAM4 SerDes for optical modules and scale-up links. The Universal Memory Interface (UMI) lets one ASIC connect to DDR, GDDR or HBM memory chiplets. The company is also developing NuLight electro-optical chiplets.

• NuLink die-to-die PHY: supports BoW, UCIe and simultaneous bidirectional signalling.
• NuLink-SP and NuLink-AP: variants for standard organic substrates and silicon interposers.
• NuLink-XS: low-power parallel chip-to-chip interface with reach up to 100 mm on the same PCB.
• NuLink-XD: configurable-reach PHY based on 224G PAM4 SerDes for optical modules and scale-up links.
• Universal Memory Interface: connects one ASIC to DDR, GDDR or HBM memory chiplets.
• NuLight chiplets: electro-optical interconnect chiplets under development.

A Vietnamese chip design team building an AI accelerator can license NuLink to connect compute and memory chiplets without advanced interposers. An OSAT or packaging facility in Vietnam can partner on multi-die products assembled on organic substrates. A networking equipment developer can use NuLink-XD for optical module links.

NuLink-SP delivers HBM-class bandwidth on standard organic packaging, which the company says cuts packaging, test and assembly costs by at least 2x and improves time to market by up to 26 weeks. Simultaneous bidirectional signalling doubles bandwidth per interface. The company claims up to 4x more HBM per package and 10x longer interconnect reach. UMI lets one ASIC design serve multiple memory configurations.

AI accelerators are hitting limits on memory bandwidth and die size, pushing the industry toward chiplets and standards such as UCIe. Advanced packaging capacity is scarce and expensive, so interconnects that work on standard organic substrates widen access. Southeast Asia, including Vietnam and Malaysia, is expanding packaging and test capacity and can benefit from chiplet designs suited to standard packaging.

Founded by Ramin Farjadrad (CEO), Patrick Soheili and Syrus Ziai; press releases are datelined Santa Clara, California. Raised a USD 145 million Series C in July 2026 at a USD 1 billion valuation, led by Seligman Ventures with Cisco Investments and Lumentum; earlier raised USD 50 million in strategic investment in January 2026. Holds more than 100 patents and has joined the Arm Total Design ecosystem.