MooresLab AI VerifAgent Agentic Chip Verification

Moores Lab AI is an agentic AI company for silicon design and verification, founded in 2025 and based in Austin, Texas. Its founders previously worked at Microsoft, ARM, Qualcomm, Intel, Tesla and NXP. The company targets the long, manual verification phase of chip projects, where building UVM environments can take six to twelve months.

VerifAgent automates verification work from specification to signoff: it generates test plans, UVM testbenches, assertions and coverage models, and helps debug multi-file issues. DebugAgent and CoverageAgent complement it, while the MooreIP and MooreSoC families extend the approach to IP development and SoC integration. The platform works with Synopsys, Cadence and Siemens tools, is LLM-agnostic and can run on-premises with the custom MooreLLM. The company states it is deployed at more than 15 chip companies worldwide.

• VerifAgent: generates test plans, UVM testbenches, assertions and coverage models from specifications.
• DebugAgent and CoverageAgent: assist root-cause debugging and coverage closure as floating licenses.
• MooreIP and MooreSoC: extend automation to IP development and SoC architecture, integration and verification.
• EDA tool integration: works with Synopsys, Cadence and Siemens flows without workflow changes.
• Flexible LLMs: supports Azure OpenAI, Anthropic on AWS, Mistral, Llama and the on-premises MooreLLM.
• Engagement models: tool licences, forward-deployed engineers or full verification-as-a-service.

A Vietnamese design services company can use VerifAgent to build UVM environments faster for overseas customer IP. A local fabless startup can outsource block verification through the verification-as-a-service model. University chip design labs can pilot agentic verification to train engineers on modern flows.

The company reports productivity gains of 92-97% and up to 86% lower verification costs. Manual UVM verification of six to twelve months can be cut to under a month, and its Verification-as-a-Service delivers a complete UVM environment in under 45 days. Existing EDA flows stay unchanged, and on-premises LLMs keep sensitive IP in-house.

Verification consumes the largest share of chip development effort, and the shortage of experienced design verification engineers is growing as custom AI silicon multiplies. Agentic AI tools that plug into existing EDA flows are emerging to close this gap. Vietnam's expanding chip design centres and service providers face the same talent constraint.

Founded in 2025 by Shelly Henry (CEO), Shashank Chaurasia (CAIO) and Sirish Munipalli (CTO); based in Austin, Texas. Lists NVIDIA, Microsoft, OpenAI and Google startup programmes, Foundation Capital and Clutch VC among backers and partners. Partnerships with Breker Verification Systems for AI-driven SoC verification and with Triple Crown.